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V.42 Modem Error Correction TMS320C5000 DSP Code

Description: this software implements the ITU Recommendation V.42 for error correction in full-duplex telephone modems by data re-transmission. V.42 is an HDLC error-protection protocol specifically for ITU V-series telephone modems, termed LAPM.
         Following the modem data pump handshake, the LAPM protocol first sends unique data patterns to connect at V.42 if the far-end is compatible. If not then transmission falls back to start-stop-bit octet formatting. On V.42 establishment, data is sent in frames of octets with a CRC (cyclic redundancy check) remainder attached. If on reception the computed CRC does not agree with that attached to the frame then its re-transmission is requested. Data rates can be asymmetric in direction.
         The software can assembled in 2 modes. In REJ-only mode, REJ being the mandatory option under V.42, on frame error detection all frames from the one rejected are resent. Then, due to latency delays, some correct data frames must be re-sent. In s-SREJ mode, which is optional under V.42 and requires the far-end to agree, only rejected frames are resent, with all correct frames in transit being retained. This mode is more efficient, leading to a gain of 2 or more in throughput in high error rate conditions, at a slight cost in increased program size and receive buffer memory. In either mode, flow control in the individual directions can be accomplished by monitoring the rate at which the transmit and receive buffers are accessed.
         The software is in the form of callable subroutines to handle initialisation and to exchange data. The code is re-entrant to facilitate multi-channel operation. The code can be operated directly at the assembler interface, but a C-callable wrapper can also be provided. This allows individual channels to be called from C. A comprehensive user's guide and example application files are provided with the code. Test results are available.

Interfaces: subroutine calls are provided so the user can both load the transmit octet buffer and empty the receive octet buffer. At the data pump interface, further subroutine calls are available to transfer data in transmit and receive directions in 16-bit blocks. To provide timer information, an additional subroutine call must be made on a regular-timed basis. At the control interface, one 16-bit control word is used to sequence operation and to report on V.42 status.

Processor Load:

(1) figures are for TMS320C54x operation with the assembler interface
(2) the MIPS figure is for 33.6kb/s full-duplex (the value scales roughly proportionate to the aggregate data rate of both directions)

Availability: NOW - sale is under licence - integration support offered