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V.42 Error Correction Software for Texas TMS320C54x/C55x DSPs

This software implements the ITU Error Correction function V.42 for data transmission by full-duplex telephone modems. V.42 is an HDLC error-protection protocol termed LAPM, formulated specifically for telephone modems. Data rates can be asymmetric in each direction.

The LAPM protocol first sends an initial handshake immediately after the modem data pump handshake is concluded to determine whether the far-end is V42-compatible. If not then transmission falls back to start-stop bit octet formatting. On V.42 establishment, data is sent in frames of octets with a CRC (cyclic redundancy check) remainder attached. If on reception the computed CRC does not agree with that attached then frame re-transmission is requested.

The software can assembled in 2 modes. In s-SREJ mode, provided the far-end is compatible, any frames rejected are resent singly which is more efficient and leads to a factor of or 2 or more gain in throughput under high frame error rate conditions. In REJ mode, frames are resent from the last one correct which is less efficient. However the program size is somewhat less and the receive buffer memory can be significantly reduced. In both modes, flow control in the transmit and in the receive directions can be automatically and separately accomplished by the rate at which the transmit and receive buffers are accessed.

The software is in the form of callable subroutines to handle initialisation and to exchange data between the user interface and the modem data pump interface of the V.42 function. Data memory is offset-addressed, so making the code re-entrant and suitable for implementing multiple V.42 functions per DSP. A comprehensive user's guide is supplied with the code. Test results are available.

Interfaces: at the user data interface, subroutine calls are provided so the user can both load the transmit octet buffer and empty the receive octet buffer. At the data pump interface, further subroutine calls are available to transfer data in transmit and receive directions in 16-bit blocks. To provide timer information, an additional subroutine call must be made on a regular-timed basis. At the control interface, one 16-bit control word is used to sequence operation and to report on V.42 status.

DSP Load:

• MIPS: 2.77

• Data memory: 2.2k words (s-SREJ mode) or 1.3k words# (REJ mode)

• Program memory: 1.9k words (s-SREJ mode) or 1.7k words (REJ mode)

The MIPS figure is for 33.6kb/s full-duplex - the value scales roughly proportionate to the aggregate data rate of both directions (# with reduced buffer size)

Availability: Now - sale is under licence - integration support offered